Today's integrated circuits include a vast number of devices. Smaller devices and shrinking ground rules are the key to enhance performance and to reduce cost. As FET (Field-Effect-Transistor) devices are being scaled down, the technology becomes more complex, and changes in device structures and new fabrication methods are needed to maintain the expected performance enhancement from one generation of devices to the next. The mainstay material of microelectronics is silicon (Si), or more broadly, Si based materials. One such Si based material of importance for microelectronics is the silicon-germanium (SiGe) alloy.
There is a great difficulty in maintaining performance improvements in devices of deeply submicron generations. Therefore, methods for improving performance without scaling down have become of interest. One general approach for improving performance is to increase carrier (electron and/or hole) mobilities in FETs. A promising avenue toward better carrier mobility is to modify the semiconductor where the current conduction takes place. It has been known, and recently further studied, that tensilely or compressively stressed semiconductors have intriguing carrier properties. In particular, improvement in the electron mobility has been achieved in a silicon (Si) channel NFET under tensile stress, as described in U.S. Pat. No. 6,649,492 B2 to J. O. Chu entitled “Strained Si Based Layer Made By UHV-CVD, and Devices Therein” incorporated herein by reference. Similarly for hole enhancement, compressively-stressed Si and SiGe have yielded high hole mobilities. Combination of tensilely and compressively stressed SiGe regions in the same wafer have been already described in patents and the technical literature, for instance, in U.S. Pat. No. 6,963,078 to J. O. Chu “Dual Strain-State SiGe Layers for Microelectronics”, and “High speed 45 nm gate length CMOSFETs integrated into a 90 nm bulk technology incorporating strain engineering” V. Chan et al., IEDM Tech. Dig., pp. 77-80 , 2003, and “Dual stress liner for high performance sub-45 nm gate length SOI CMOS manufacturing” Yang, H. S., IEDM Tech. Dig., pp. 1075-1078, 2004, all three of these incorporated herein by reference.
Optimally, one would like to have integrated circuits such that the channel of electron conduction type devices, such as NFET, is tensilely stressed, while the channel of hole conduction type devices, such as PFET, are compressively stressed. However, global approaches in employing stress to enhance performance, such as the use of SiGe alloys, have problems with defected materials. Accordingly, so called locally induced stress approaches have been introduced more recently. In these, stress with the appropriate sign is introduced into the channel by means that are local to the device structures, for instance, by using the gate to impart stress into the channel as described in U.S. Pat. No. 6,977,194 to Belyansky et al. entitled “Structure and method to improve channel mobility by gate electrode stress modification” incorporated herein by reference. In other local approaches, stressed conformally deposited dielectric layers are utilized. Unfortunately, all the techniques used to date for achieving such stressed channels lack full satisfaction, either due to their complexity, or due to their relative ineffectiveness.